Precision timing
SiT95924
Quad PLL, 24-output Network Synchronizer
The SiT95924 network synchronizer offers programmable quad fractional frequency translation with flexible input to output frequency translation options. The high performance DPLLs support up to 4 differential or 8 single-ended input clocks and provide 24 clock outputs. The clock outputs can be derived from any of the 4 PLLs in a fully flexible manner. This device is fully programmable with the I2C/SPI interface or an on-chip one time programmable (OTP) non-volatile memory for factory pre-programmed devices.
| "Specs" | "Value" |
|---|---|
| Operating Temperature Range (°C) | -40 to 85 |
| Package Type (mm²) | 15x15 mm, 112-pin LGA |
| Number of Inputs | 4 Differential, 8 Single Ended |
| Number of Outputs | 24 |
| Input Type | LVCMOS, LVDS, LVPECL, CML, HCSL |
| Input Frequency Range | 0.5 Hz to 2.1 GHz (Differential) |
| Output Type | LVPECL, CML, HCSL, LVDS, LVCMOS |
| Output Frequency Range | 0.5 Hz to 2.94912 GHz (Differential) |
| Number of PLL/Clock Domains | 4 PLL |
| Phase Jitter (rms) | 25 fs RMS (typ.) at 312.5 MHz (12 kHz to 20 MHz with 4 MHz high-pass filter) |
| Repeatable Input-Output Delay | ±225 ps |
| Frequency Control DCO | 0.001 ppt (all outputs) |
| Phase Control DCO | <1 ps (all outputs) |
| Internal ZDB Mode | <0.5 ns input to output delay variation |
| Programmability | NVM OTP, External EEPROM, Partial autonomous, SPI/I2C |
| Features | Wander attenuation loop bandwidth down to 0.09 mHz, ±25 ps maximum phase hit, JESD204B/C support |
| Availability | Production |
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112 pin, 15 mm x 15 mm LGA package
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SiT95924 Functional Overview
- Best-in-class 75fs 12k-20M integrated jitter for quad PLL
- JESD204B/C support for data converter clocks
- 1 PPS input / output support with sub 20s best-in-class lock time
- Best-in-class hitless switching performance with <25 ps hit
- External EEPROM support and on-chip OTP
- Frequency DCO (0.001 ppt) and phase control DCOs (<1 ps resolution)
- Internal ZDB on all PLLs with < ±500 ps input to output delay across temp
- G.8273.2 / IEEE 1588 assisted holdover
- Independent VDDO (3.3 / 2.5 / 1.8 V)
- Fully flexible output and input mux
- SerDes
- Optical Transport Network (OTN) Clocking for Framers, Mappers & Processors
- Wireless Networks
- Datacenter Switches & Routers
- 4G / 5G RRH, DU
- IEEE 1588 Precision Time Protocol (PTP)
- Broadcast Video
- Medical Monitoring
- Test & Measurement
- Top of Rack / Leaf Switches
SiT95924 IBIS Model – Download .ibs file
SiT95924 Evaluation Board (EVB) HW User Manual – Configure and evaluate device performance
SiT95924 GUI User Manual – Configure device and verify the performance of the chip
Setup SiTGUI SiT95924 Software – Download software .zip file
| Resource Name | Resource Type | Date | Format | Size |
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