Precision timing
SiT92310
20 Output DB2000QL Equivalent with 85/100Ω Terminations
The SiT92310 is a HCSL-LP, 20 Output differential Fan Out buffer, that meets or exceeds all the performance requirements of the Intel DB2000QL specification. They are suitable for PCI-Express Gen1 to Gen7 or QP/UPI applications.
The SMBus interface and multiple output-enable pins allow the configuration to control all 20 outputs individually.
It is packaged in a compact QFN package and uses a standard pin configuration.
| "Specs" | "Value" |
|---|---|
| Operating Temperature Range (°C) | -40 to 85 |
| Package Type (mm²) | 10x10 mm, 72-pin QFN |
| Buffer Type | PCIe Fanout |
| Number of Inputs | 1 |
| Number of Outputs | 20 Differential |
| Input Type | HCSL |
| Input Frequency Range | 1 Hz to 400 MHz |
| Output Type | HCSL-LP |
| Output Frequency Range | 1 Hz to 400 MHz |
| Additive Phase Jitter (rms) | 8 fs (PCIe Gen7 @100 MHz) |
| Propagation Delay, Typical | 0.75 ns |
| Output-Output Skew, Typical | 50 ps |
| PCIe Support | Gen1 to Gen7 |
| Output Enable | Yes |
| Availability | Contact SiTime |
-
10x10 mm, 72-pin QFN Clock Buffer package
- HCSL-LP outputs with Zo = 85/100 Ω
- Saves power and board space - no termination resistors required.
- Supports PCIe and QP/UPI applications
- Spread spectrum compatible; tracks spreading input clock for low EMI
- Additive phase jitter
- Fclk=156.25 MHz (10k-20M) band ~37 fs (Typical)
- Fclk=100 MHz after PCIE Gen5 (CC) filter ~12 fs RMS
- Fclk=100 MHz after PCIE Gen7 filter ~8 fs RMS
- Additive phase jitter after DB2000Q filter ~10 fs RMS (Typical)
- Programmable output slew rate control
- Output to Output Skew < 62 ps
- 3.3 V core and IO supply voltages
- Hardware-controlled low power mode (PDN)
- Current consumption: 185 mA Typical with all 20 outputs enabled at 100 MHz, driving a 10 inch T line and 2 pF load on each output.
- Microserver and Tower Server
- Rack Server
- Storage Area Network (SAN)
- Host Bus Adapters (HBA)
- Network Attached Storage (NAS)
- Solid-State Drives (SSD)
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